For a cell of dynamic random access memories (hereinafter referred to as a DRAM), there has been hitherto widely employed a memory cell of a one transistor one capacitor type using one switching transistor and one capacitor. A recent trend toward miniaturization of memory cells for achieving a high density of DRAM is so remarkable that it is now difficult to provide adequate capacitance of on a scaled down capacitor unless a three-dimensional structure is used.
To meet the requirement in this field of techniques, there has been developed a DRAM where stacked capacitors are buried in grooves. For instance, a BSCC (buried stacked capacitor cell) has been proposed in Nikkei Micro Devices Independent Volume No. 1, entitled "The Whole Aspect of 4M DRAM Starting Toward Practical Applications" p. 215-220, (1987).
FIG. 2 shows a sectional view of such a known semiconductor memory device. On part of a P-type silicon substrate 101 is formed a field oxide film 102. A groove 103 is formed in the silicon substrate 101 at the end of the field oxide film 102. The groove 103 has a thick oxide film 104 formed in the inner walls thereof. A capacitor consisting of a capacitor electrode 106 consisting of a polysilicon film, a dielectric thin film 107 and a cell plate electrode 108 is formed on the thick oxide film 104. The capacitor electrode 106 is connected with one diffused layer 111a of an adjacent transfer gate transistor at a contact 105 thereof. The transfer gate transistor is constituted of an oxide film 109, a data electrode 110 and diffused layers 111a, 111b forming a source and a drain, respectively. The diffused layer 111b of the transfer gate transistor is connected to a bit wire 114 through a contact hole provided in a layer insulation film 112. The transfer gate transistor and the capacitor are protected with a passivation film 115.
The capacitor electrode 106 is formed by solid phase diffusion of an impurity from an impurity-containing silicate glass film in the polysilicon film in an atmosphere of an inert gas. (See Journal of Electrochemical Society, August, 1972, Vol. 119, No. 8, pp. 1080-1084.)
However, the above-described solid phase diffusion technique involves the problem that the impurity cannot be satisfactorily introduced into the polysilicon film in the groove.
If the thermal treating temperature is raised or the thermal treating time is prolonged in order to permit the impurity to be introduced sufficiently in the polysilicon, the junction at the time of formation of an N.sup.+ diffused layer portion or the contact portion with the cell capacitor becomes deep, with an attendant problem that the element separability between cells is lowered.
Furthermore, when N.sub.2 is used as an atmospheric gas for the thermal treatment, regions where the concentration of the impurity is high will be locally formed in the silicate film after the thermal treatment, resulting in a non-uniform concentration distribution of the impurity in the polysilicon film. This leads to the problem that a deposit in the form of a film or fine crystals serving to suppress the diffusion of the impurity is formed at the interface between the silicate film and the polysilicon film.
The present invention has for its object the provision of a method for fabricating a semiconductor device wherein an impurity can be satisfactorily introduced into a polysilicon film.
The invention has for another object the provision of a method wherein an impurity can be introduced into a polysilicon film in a groove without lowering the element separability between cells.